1. Field of the Invention
The present invention relates to a method of forming a transistor on an SOI wafer and has a structure capable of preventing a potential of a support substrate below a buried insulating film from significantly affecting the characteristics of the transistor. More specifically, the present invention relates to a transistor having a so-called gate sub-connection structure in which a gate electrode and a body region of the transistor are connected to each other.
2. Description of the Related Art
FIGS. 6A to 7C illustrate a conventional method of manufacturing an SOI transistor, and FIGS. 8A and 8B are respectively a top view and a sectional view of the structure of the conventional SOI transistor. Conventionally, a transistor is formed by using a wafer in which a P-type semiconductor film 51 is formed on a P-type support substrate 53 via a buried insulating film 52.
In the structure of the conventional SOI transistor that is formed on the semiconductor film 51 formed on a support substrate 53 via a buried insulating film 52, the transistor is formed on the semiconductor film 51 in a region surrounded by a LOCOS region 58 reaching the buried insulating film as shown in FIG. 8B, and each transistor is completely isolated by the LOGOS region 58. In the case of an N-type transistor, since the semiconductor film 51 is of a P-type, the transistor is formed by implanting N-type ions into source/drain regions 64 and 76, as shown in FIG. 8A. On the other hand, in the case of a P-type transistor, the transistor is formed by implanting N-type ions into the semiconductor film 51 surrounded by the LOGOS region 58, and implanting P-type ions into source/drain regions 63 and 75 under the condition that the semiconductor film 51 is kept in an N-type as shown in FIG. 8A. Then, potentials of body regions 82 and 83 below gate electrode 60 are controlled through body contact regions 61 and 62, and body contacts 65 and 66. In order to achieve a higher speed operation of the transistor, in the case of the P-type transistor, the gate electrode 60 and the body contact 65 of the P-type transistor are connected to each other through a wiring layer 69. In the case of the N-type transistor, the gate electrode 60 and the body contact 66 of the N-type transistor are connected to each other through a wiring layer 70.
Further, the manufacturing method is shown in FIG. 6A to 7C. As shown in FIG. 6A, patterning and etching are conducted so as to imprint an alignment mark on the semiconductor film 51 formed on the support substrate 53 via the buried insulating film 52. Next, as shown in FIG. 6B, a thermal oxide film 54 is formed, and a resist 56 is applied thereto. Then, alignment and exposure to light are conducted, and patterning for the purpose of implanting an N well 55 is connected. Next, ions are implanted using the resist 56 as a mask to form the N well 55. At this time, the energy of ion implantation is controlled so that the semiconductor film can have the peak of a concentration distribution. Thereafter, heat treatment is conducted so that the implanted ions are activated and diffused. Then, as shown in FIG. 6C, nitride films 57 are formed on the thermal oxide films 54 and are subjected to patterning and etching. Then, as shown in FIG. 6D, thermal oxidation is performed to form the LOCOS region 58. At this time, thermal oxidation is conducted so that the LOCOS region 58 reaches the buried insulating film 52. After forming the LOGOS region 58, as shown in FIG. 7A, gate oxide films 59 are formed and gate electrodes 60 are formed. Although not shown in FIG. 7A, in the transistors shown in FIG. 8A, ions are implanted into source/drain regions 63, 64, 75, and 76 and body contact regions 61 and 62, and an interlayer insulating film 71 is formed. Subsequently, as shown in FIG. 7B, the interlayer insulating film 71 is patterned and etched to form the gate electrodes 60, body contacts 80 and 81 of the body contact regions 61 and 62 and, although not shown in FIG. 7B, contacts 67, 68, 77, and 78 of the source/drain regions of FIG. 8A.
Next, as shown in FIG. 7C, metal is formed into a film and is patterned to form wirings 69 and 70. In the transistor of the gate sub-connection structure, the respective gate electrodes 60 are connected to the body contact regions 61 and 62.
In this case, the buried insulating film 52 is disposed between the support substrate 53 and the semiconductor film 51, 50 that a potential of the support substrate 53 is in a floating state. In the SOI transistor, the potential of the support substrate 53 affects the characteristics of the transistor, so that it is required to fix the potential of the support substrate 53. The potential of the support substrate 53 is generally set by attaching the support substrate 53 to a conductive base using a conductive adhesive when being mounted in a package, so that the potential is taken from the base. Generally, the support substrate is connected to a ground terminal or a power source voltage terminal.
There is also another method of taking the potential of the support substrate side from the semiconductor film side. Specifically, a through-hole is provided so as to reach a part of the support substrate 53 through the semiconductor film 51 and the buried insulating film 52, thereby taking a potential. In this case, in the same way as in a method of taking a substrate potential of a bulk transistor, a through-hole is provided on the periphery of the transistor so as to reach a part of the support substrate 53 through the semiconductor film 51 and the buried insulating film 52, and the potential of the support substrate 53 is taken.
According to the conventional method of forming an SOI transistor, since there is a buried insulating film between a support substrate and a semiconductor film, a transistor on the semiconductor film is not electrically connected to the support substrate, and the potential of the support substrate is floated. However, in a complete depletion type SOI transistor and the like, a semiconductor film is entirely depleted in the thickness direction and depletion reaches a buried insulating film. Therefore, the potential of the support substrate greatly affects the characteristics of the transistor, and a change in potential of the support substrate exhibits the same characteristics as that of a back gate effect of a bulk transistor. Therefore, it is required to fix the potential of the support substrate. Generally, according to the method of fixing the potential of the support substrate, the support substrate is attached to the conductive base by the conductive adhesive when being mounted in the package, and the potential of the base is fixed, so that the potential of the support substrate is fixed. The potential of the support substrate is connected to the ground terminal or the power source voltage terminal.
However, even if the body contact region is connected to the gate electrode to achieve the gate sub-connection structure, since the potential of the support substrate does not change, it is difficult to obtain ideal subthreshold characteristics.
Furthermore, in the SOI transistor from a structural view, there is a back side transistor in which a support substrate is considered as a gate electrode, and a buried insulating film is considered as a gate oxide film. Thus, a threshold voltage of the back side transistor is low. Then, when the power source voltage increases, the back side transistor is turned ON to decrease a withstand voltage thereof.
Further, as the method of taking a potential of the support substrate side from the semiconductor film side, the through-hole may be formed so as to reach a part of the support substrate through the semiconductor film and the buried insulating film to thereby take a potential. However, also in this system, the potential of the entire support substrate changes, which not only makes impossible to obtain ideal subthreshold characteristics but also causes characteristic change in a circuit for which a back gate effect is not required. This leads to a defective circuit operation.